NVIDIA Might Shift To Improved FOPLP Packaging For A.I. Chips In 2025 : US Pioneer Global VC DIFCHQ NYC India – Riyadh Norway Our Mind

After Microsoft and AMD had a jam packed event earlier this week, which saw Microsoft chief Satya Nadella share details of his firm’s partnership with the chipmaker for artificial intelligence computing, a fresh report from Taiwan shares that NVIDIA is working to optimize the supply chain of latest A.I. chips. NVIDIA’s Blackwell GPUs are among the best performing A.I. products on the market, and according to Taiwan’s Economy News Daily, NVIDIA’s Blackwell GB200 GPU might use panel level fan out packaging ahead of schedule in 2025.

NVIDIA Aims To Diversify Final Chip Design To Avoid A.I. Chip Shortage, Says Report

According to the report, NVIDIA is interested in relying on panel level fan out packaging, commonly called FOPLP, for the Blackwell chips. A shortage in the packaging end of the semiconductor supply chain has been an analyst worry for years, with the first questions pressing NVIDIA and its manufacturing partner TSMC’s management on the matter in 2022.

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Semiconductor fabrication is a long drawn process that first involves manufacturers like Intel or TSMC carefully depositing and printing circuits on a silicon wafer and ensuring that strict cleanliness standards are followed. After the chips are made, they have to be packaged with other components to allow them to process artificial intelligence and other workloads.

Chip manufacturers can package the final product in several ways. Right now, the industry standard approach is wafer level fan out packaging. This process cuts the wafer into chips, which are then reassembled into another wafer with the added space to lay out the needed circuits.

A Samsung presentation showing the benefits of fan out packaging over its predecessors. Image: Samsung Semiconductor

Fan out packaging enables chip manufacturers to remove faulty chips from the packaging process. FOPLP, or fan out panel level packaging, is an advanced FOWLP variant. The primary difference between wafer level and panel level packaging is that instead of reassembling the cut chips on a wafer, they are reassembled on a larger panel. This allows manufacturers to package a much larger number of chips, reducing the cost of the packaging process. It also improves packaging efficiency as chips on the edges of the panel can be packaged as well.

According to the Economic Daily, Taiwanese firms such as PowerTech and Innolux are developing panel level packaging technologies. It quotes Innolux representatives as saying that panel-level packaging can enter mass production by the end of this year. Additionally, the report adds that NVIDIA’s capacity for CoWoS (chip on wafer on substrate) packaging for the Blackwell products is tight. As a result, rumors share that Blackwell GB200 might also start to use FOPLP ahead of schedule next year in 2025 as opposed to the initial 2026 timeline.

The report also mentions the use of a glass substrate, which should enable chips to withstand higher temperatures for longer and maintain their optimal performance. Finally, Economy Daily’s sources believe that roughly 420,000 GB200 chips should be delivered in H2, with output expected to scale up to two million units in 2025.

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