The widespread boom in the use of AI chips benefits many companies that often do not come into the limelight. Most observers often credit GPU designer NVIDIA Corporation as being responsible for leading the AI charge, but the reality is that there is a complex web of companies stretching from Asia to the US that play important roles throughout this supply chain.

With the UN estimating that the AI market is expected to touch $4.8 trillion by 2033, it is important to understand which firms drive the AI supply chain. These range from wafer manufacturers headquartered in South Korea and Germany to design software providers in the US, Asian chemical companies and semiconductor manufacturers in Taiwan.

The Beginning of An AI Chip – Inside The Software & Hardware Of Electronic Design Automation (EDA) Companies

Before AI chip designers such as NVIDIA can ship out their designs to semiconductor manufacturers, they must create them. Contrary to the popular belief that the global semiconductor supply chain is concentrated in Asia, most EDA firms are in America. Consequently, the journey of an AI chip starts with products made by an American or European company.

EDA companies contribute to chip design at the supply chain’s start and post-manufacturing performance verification. Consequently, their products are essential to ensuring that AI chips meet high-end performance requirements.

At the start, or the extreme upstream, EDA providers such as Cadence Design Systems, Synopsys, Ansys and Siemens provide the tools to design a chip and the manufacturing process used by manufacturers.

EDA simulation tools allow chip designers to predict their products’ performance during the design process and tweak their designs before the expensive fabrication stage. Like the broader chip manufacturing and design industry, the EDA industry is dominated by a handful of players. 70% of the market is controlled by three companies, Cadence, Synopsys and Siemens.

Cadence, a firm that earned $4.6 billion in revenue in its latest fiscal year, provides products for integrated circuit (IC) design, IC verification, printed circuit board (PCB) design, design verification, thermal analysis and other areas of semiconductor design and development. It is somewhat larger than Synopsys, which earned $3.2 billion in revenue.

Yet, both (“We depend on a single supplier or a limited number of suppliers for certain hardware components,” for Cadence and “Increased dependence on a sole supplier for certain hardware components,” for Synopsys) are reliant on a single supplier for key components which places the entire semiconductor supply chain at the risk of disruption should a few companies fail to deliver.

Cadence’s Genus, Synopsys’ Fusion and Siemens’ Oasys systems work at the register-transfer-level (RTL) phase of semiconductor design where designers use low-level programming language to map out the flow of data within a chip. This allows them to map out data flow and simulate a chip’s performance during the design phase to tweak out anomalies.

Yet, today’s chip designs, which involve billions of transistors (Apple’s latest M4 chip features 28 billion transistors) means these transistors operate in groups in different domains with differing frequencies and voltages. Communication between these domains, called clock domain crossing (CDC) can introduce errors.

While CDC errors occur across domains within them, reset domain crossing (RDC) errors can also emerge in the same domain. RDC errors are when elements in a chip operate on asynchronous reset profiles where they shift to a default state in non-conformance to each other. To navigate these errors, Cadence’s Conformal Litmus and Jasper CDC App enable engineers to check CDC and RDC and rectify errors. Synopsys offers VC SpyGlass while Siemens offers Questa RDC verification and CDC analysis platforms.

RTL and CDC are in the early stages of AI chip design, and RTL’s mapping accuracy to the final circuit map (netlist) is a key design aim. Cadence’s Conformal Equivalency Checker (EC), Synopsys’ IC Validator and Siemens’ Calibre Circuit Verification allow designers to verify that the netlist is an accurate representation of RTL, a process called layout versus schematic (LVS) checking. These tools are often also used to verify the design’s compatibility with the manufacturing process. EDA firms also provide emulation and prototyping systems to designers to allow them to ensure their designs meet market requirements.

These two errors, along with LVS checking, form the start of the AI chip supply chain. At the design’s final stage is a IC package which protects the chip and allows it to be connected to a printed circuit board (PCB). Within a package, multiple chiplets designed to perform specific functions (such as logic processing or memory storage) are often integrated. Cadence’s Integrity 3D-IC, Synopsys’ Die-to-Die IP and Siemens’ Innovator3D IC and Xpedition Package Designer platforms and the Allegro X Advanced Package Design Platform aid AI chip designers in this final stage.

Finally, chip designers’ requirement to accommodate billions of transistors in a single chip means manufacturers must design manufacturing processes capable of doing so. This bit is relevant to AI chip manufacturing and relates to the firms discussed below. Modern-day chip manufacturing characterizes advanced manufacturing processes as sub-7-nanometers, including technologies such as 5nm, 3nm and the leading-edge 2nm.

These manufacturing technologies require advanced extreme ultraviolet (EUV) machines to reduce circuit size and accommodate large transistor amounts. The smaller circuit sizes, facilitated by advancements such as fully depleted silicon on insulator (FD-SOI) technology, reduce current leakage and higher speeds at low voltages. However, they introduce problems that require greater accuracy and complex operations such as multi-patterning.

To help chip manufacturers overcome these constraints, the EDA companies work with firms such as TSMC to certify design tools which will design products eventually manufactured by the latest manufacturing processes.

An AI Chip Comes To Life After Disks Of Refined Sand Are Coated With Chemicals & Bombarded With Light To Print Transistors

With the design of our AI chip now complete, the next phase is perhaps the most crucial as well as the riskiest. Taiwan’s Taiwan Semiconductor Manufacturing Company (TSMC) is responsible for nearly all the world’s advanced AI chip manufacturing. NVIDIA’s Blackwell AI GPUs, which are the most advanced AI chips in the world, are manufactured on a custom variant of TSMC’s N4 node. Virtually all N4 production is in Taiwan, with TSMC’s facilities in Arizona expected to scale N4 production soon.

Manufacturing an AI chip first requires TSMC to procure silicon wafers. While the AI chip supply chain faces a second risk and bottleneck due to TSMC’s dominance, procuring wafers does not face similar risks. Key suppliers in the industry are FST, GlobalWafers, Shin-Etsu Handotai, Siltronic AG, SK siltron and SUMCO, and together, they account for the majority of the world’s wafer supplies.

To manufacture AI chips, TSMC most likely relies on 12-inch or 300mm wafers since its N4 production occurs in Fab 18, located in Tainan, Taiwan. Epitaxial wafers, or those with a single crystal silicon layer on a silicon substrate, are likely used to manufacture AI chips. The wafer supply chain is diverse, with the largest suppliers mentioned above headquartered in Germany, South Korea and Japan. GlobalWafers has a facility manufacturing epitaxial wafers in TSMC’s hometown of Hsinchu, Taiwan.

Yet, while wafer suppliers are abundant, the advanced equipment used in the first and most crucial stage of manufacturing AI chips on a silicon wafer is supplied only by one firm, ASML. This part of the manufacturing process is called lithography, and it involves imprinting the wafer covered with photoresist with chip designs transferred onto a mask after design through EDA.

Semiconductor fabrication is one of the most complex processes in the world. It can broadly be narrowed down to seven steps to analyze the role of the chemical and materials supply chain. Before a fabrication company can transfer a design to a wafer, it is first transferred to a photomask in a process called the tape-out. On this front, TSMC is independent of suppliers as it claims to be the world’s largest photomask manufacturer.

While manufacturing masks is a relatively simple process compared to the complexity of chip fabrication, the end product, which is necessary to transfer circuit design to the photoresist and finally to the wafer, is crucial.

Equally important is the photoresist, which performs the heavy lifting in the design transfer process. On this front, TSMC relies on external suppliers. It has already suffered once from faulty photoresist when, in 2019, the firm took a $550 million hit due to contaminated photoresist.

Shin-Etsu Chemical and Sumitomo Chemical are the firm’s likely current photoresist (a material coated on the wafer to transfer the pattern from the photomask) suppliers, according to a cross-analysis of its historical and recent annual reports.

Tokyo Ohka Kogyo (T.O.K) and JSR are two additional Japanese firms that are part of the photoresist supply chain. The pair is crucial for leading-edge manufacturing processes that rely on EUV since EUV photoresists have to contend with fewer photons and less absorption compared to traditional DUV (deep ultraviolet) fabrication.

The criticality of photoresists in the semiconductor supply chain cannot be overstated. After all, the first stage of the manufacturing process uses lithography to transfer the chip design from the photomask to the photoresist which means that the right photoresist is indispensable for perfect chip fabrication.

While ASML dominates lithography equipment, photoresist coating and developing equipment is one of the hottest markets in the semiconductor supply chain which appears to be evolving right now.

Traditional photoresist applications rely on spinning wafers in a liquid to deposit a liquid photoresist. The process includes preparing the wafer surface, wet photoresist coating, soft baking, photomask alignment and exposure (to UV or EUV light for design transfer from the photomask), post-exposure baking to harden the photoresist on the wafer, excess photoresist removal and hard baking.

The problems generated by EUV manufacturing have led to Lam Research promoting its Aether dry photoresist technology as a superior option over the current technologies offered by its Japanese rivals. Lam contends that its technology relies on vapor deposition to deposit a metal photoresist on the wafer.

While photoresist manipulation and application involve chemicals, it is far from the only portion of an AI chip’s fabrication to rely on them. But before we get to them, two additional critical supply chains merit a mention. After the photoresist’s application on the wafer, the photomask is placed in the scanner (or lithography machine made by ASML) and exposed to light to transfer the AI chip design on the photoresist.

Since integrated circuits are fabricated at the nanoscale, even the slightest impurities can distort a design. A pellicle is used to protect the photomask’s surface from impurities by placing it on top of it. As a result, any impurities accumulate on the pellicle, and their shapes are not transferred onto the photoresist and subsequently to the wafer.

The pellicle supply chain, along with the photoresist supply chain, has also been shaken by EUV. EUV pellicles have to be temperature tolerant and not absorb light, among other characteristics. As a result, once EUV machines entered the market, pellicle manufacturers could not meet market needs. In its 2021 online technology symposium, TSMC confirmed its use of in-house EUV pellicles and outlined that it aimed to double its EUV pellicle capacity by year-end.

The next phases of semiconductor manufacturing, namely etching, deposition, chemical mechanical polishing (CMP), metallization and ion implantation rely extensively on the chemical and gas supply chains.

Starting with etching, this phase in semiconductor fabrication involves removing excess material from the wafer after the photomask is used to print the design on the wafer with the help of the photoresist. Etching removes the undesired wafer material and the photoresist is removed during etching or through stripping.

Modern-day chip fabrication relies on plasma etching, where the wafer with the photomask is placed in a vacuum chamber. In this chamber, different gases, such as argon, oxygen and fluorine, are used. Noble gas compounds are preferred since they are likely to generate free radicals that bombard the substrate and react with it to remove unnecessary materials and create circuit patterns.

Argon can also be used as a standalone gas in combination with noble gas compounds for greater efficiency, while helium is often relied on to cool the wafer during the etching process. Gasses such as carbon tetrafluoride, chlorine and sulfur hexafluoride are used to detect light emissions during the process and decide when to stop etching.

For some cases of FinFET fabrication, Hydrogen Bromide is used, while oxygen also plays a role in removing the photoresist (or photomask) after etching. These only scratch the surface of the myriad of gasses used throughout fabrication, with others being hydrogen chloride, nitrous oxide, ammonia and carbon dioxide, among others.

Along with etching, deposition, chemical mechanical planarization (CMP) and metallization are other key processes for manufacturing an AI chip. Without deposition, there would be no etching as deposition places material on the wafer for AI chip circuit pattern design. Just as etching relies on plasma to dissolve regions of the substrate, deposition can rely on it to deposit material. For advanced manufacturing, chemical vapor deposition and its variants, such as atomic layer deposition (ALD) and molecular layer deposition, are used.

Raw materials for these processes include organic compounds such as alkanes, inorganic metal oxides of metals such as aluminum and zinc, silicon compounds, carbon compounds and high-k dielectrics such as hafnium oxide. Ion implantation is similar to deposition except that it aims to introduce conductivity to the substrate, and CMP involves regular wafer cleaning during fabrication to ensure a flat surface for optimum fabrication.

CMP is important when discussing the AI chip supply chain since its raw material suppliers include slurry, pad and disk manufacturers. On the other hand, deposition, etching and metallization rely on chemical, gas and metal suppliers.

Consequently, the chemical and gas supply chain is perhaps the backbone of the AI chip supply chain. Major players that potentially supply TSMC include DuPont, Fujifilm, Merck, Air Liquide, Central Glass, Entegris, Nippon Sanso, BASF, Air Products and Kanto-PPC, Inc.

Unlike key areas such as EUV photomask and lithography machinery, the gas and chemical supply chain for AI chip fabrication is quite diversified. Within this list, DuPont has one of the widest portfolios, covering chemicals and lithography materials. Its products include chemicals used in atomic layer deposition, pads and slurries for CMP, etch residue removers, and CMP cleaners.

Fujifilm also provides CMP cleaners and slurries along with ammonium fluoride and hydrogen fluoride etchants. BASF’s SELECTIPUR products cover metal and non-metal etch products, while the FOTOPUR products cover post-etch cleaning. Recent reports have also indicated that TSMC is relying on diamond disks for the CMP process.

As is with DuPont, Merck also has a diversified portfolio of products used throughout the AI chip fabrication and manufacturing process. These include fluorine gasses used in patterning, deposition materials, wafer polishing slurries, fluoride gasses for etching and high-k material ALD precursors. Japan’s Kanto-PPC also provides etchants, etch cleaners, CMP cleaners and CMP slurries.

Shifting towards pure-play gas suppliers, Japan’s Nippon Sanso and France’s Air Liquide are among the largest industrial gas suppliers in the world. Air Liquide’s gasses cover etching and ALD, while Nippon Sanso’s portfolio covers all steps of the fabrication process, from lithography to etching, deposition and doping. Silicon wafers are tested for defects through equipment provided by firms such as Teradyne,

The Chip Is Made (Or The Die Is Cast?), But The Journey Is Far From Over – Enter CoWoS

With front-end-of-line (FEOL) fabrication complete and interconnects added via back-end-of-line (BEOL) followed by passivation, our wafer is ready to be sliced into advanced AI chips. However, these chips cannot be used in a data center for AI computing.

In order to be usable, they must be packaged into a workable form for final integration into a PCB. This process is called packaging, and for NVIDIA, it initially emerged as a significant bottleneck in the AI chip supply chain. The packaged chip (or die) is called an integrated circuit (IC), and TSMC is NVIDIA’s primary packaging partner,

When compared to the tedious process of manufacturing a chip die, packaging is a relatively simple affair. A typical chip-on-wafer-on-substrate (CoWoS) package can broadly be divided into a dozen parts. At the top of the package is the protective material that protects the AI chip die and high-bandwidth memory (HBM) below it from the lid, which seals the package from the top. Key NVIDIA HBM memory suppliers include SK hynix and Micron.

Within the region covering the AI chip and HBM a liquid molding compound (LMC) and non-conducting film (NCF) are applied to ensure they maintain position within the package and do not leak current into their surroundings. Below the HBM is an underfill material followed by a Redistribution Layer (RDL) in some variants. Beneath the RDL is more underfill, followed by a silicon interpose and C4 bumps part of the circuitry to connect the SoC and HBM to the substrate at the package’s bottom.

The supply chain for these materials is quite diverse and includes several firms we’ve mentioned above. For instance, Dow and DuPont provide the insulating material at the top of the package. They are met by Indium, 3M and Henkel AG & Co. KGaA. Henkel and Japan’s Resonac Holdings Corporation also supply NCF, LMC and underfill materials. Within the packaging supply chain, the one for LMC and RDL is the most diversified. Along with Resonac and Henkel, Japan’s Sumitomo Bakelite Co., Ltd., Panasonic and Nagase & Co., Ltd. are also LMC suppliers.

Next up is the RDL supply chain. The RDL is one of the most important components of a semiconductor package and is a key differentiating factor between different CoWoS packaging techniques. For this piece, we will focus on the CoWoS-R process, which includes only the RDL placed on top of the wafer.

The RDL material, called photosensitive polyimide (PSPI) is supplied by Fujifilm, Asahi Kasei Corporation, JSR Corporation, HD MicroSystems Ltd., Toray Industries Inc., and TOK. The RDL sandwiches the silicon wafer. This wafer is provided by wafer suppliers noted above and is typically prepared by semiconductor manufacturers like TSMC. The wafer is also called an interposer, and its supply constraints were an early constraint in the AI chip supply chain. Recent reports also raise worries about the PSPI supply chain.

After the silicon wafer and the RDL, the next components in a CoWoS AI chip package are microballs in the controlled collapse chip connection (C4) flip chip bonding technology, solder masks, the build-up film, the substrate core, glass fiber sandwiched between the substrate cores and the solder balls at the package’s bottom.

The chip, along with the RDL material, is installed on the substrate through the flip-chip process. This process involves microballs and the C4 bump process. Three key microball suppliers are Nippon Micrometal Corporation, NIPPON STEEL Chemical & Material Co., Ltd. and Senju Metal Industry Co., Ltd. The C4 bump process places the SoC, HBM and RDL on a solder mask typically provided by Resonac, TAMURA Corporation and Taiyo Holdings Co., Ltd.

Beneath the mask is the final part of the package, the substrate. The substrate is made of a glass fiber substrate core and build-up film. Reports suggest that NVIDIA is seeking to shift towards next-generation glass substrates for its AI chips. These substrates are particularly notable for their high thermal resistance.

The ABF (Ajinomoto Build-up Film) substrate is commonly used in CoWoS packaging. Key ABF suppliers are Resonac, Doosan Corporation Electro-Materials, Mitsubishi Materials Corporation and Panasonic. An ABF substrate relies on a build-up film, and Ajinomoto Co., Inc. along with Sekisui Chemical Co., Ltd. and Taiwan’s WaferChem are key players in this industry.

However, when it comes to NVIDIA-specific AI chip substrates for packaging, Japan’s Ibiden Co., Ltd. is widely believed to be the dominant player while NVIDIA has also mentioned Kinsus Interconnect Technology Corporation, and Unimicron Technology Corporation as its substrate suppliers. For the overall packaging process, along with TSMC, ASE Group, Amkor and Siliconware Precision Industries Company Ltd. also provide packaging services.

The Final Leg – Assembly, Testing & Shipping

With the AI chip package complete, the next phase in the AI supply chain is testing and assembly. A chip package is tested before being attached to a printed circuit board (PCB). After being installed onto a PCB, the last leg is server manufacturing, after which the chips are used in data center computing for AI applications.

AI chips are tested after the silicon wafer is manufactured and after being packaged into an IC. Test equipment providers play a crucial role in this supply chain. Firms such as King Yuan ELECTRONICS CO., LTD provide wafer testing services and equipment from testing equipment providers. These providers include Japan’s Advantest Corporation, which is one of NVIDIA’s closest partners for chip testing. Advantest’s V93000 is one of the most advanced testing machines in the market, and another potential key NVIDIA supplier in the testing market is Taiwan’s Chroma ATE Inc. Chroma’s products help NVIDIA with tests that follow post-packaging tests.

These tests are called system-level tests (SLTs), and they simulate an IC’s real-world performance to detect defects ahead of time. Chroma is believed to be NVIDIA’s only SLT equipment supplier, and its latest products boast data transfer rates of up to 1Gbps. Amkor Technology and Siliconware Precision Industries Co., Ltd. (SPIL) offer key services in the final testing and burn-in tests.

The final leg of an AI chip, now integrated into a package, is with contract manufacturers and server equipment providers such as SuperMicro. Taiwan’s Hon Hai, also known as Foxconn, is a key NVIDIA server manufacturer. Along with Foxconn, Wistron also manufactures NVIDIA AI servers.

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