MIPS has made some waves in the embedded processor IP community, especially with its recent acquisition of Synopsys’s ARC processor IP business. The company has made a major comeback since filing for bankruptcy in 2020 and emerging from the downturn, shifting its focus from Microprocessor without Interlocked Pipelined Stages (MIPS) to RISC-V architecture. The company heralded the MIPS instruction set with massive success, helping accelerate it’s physical AI roadmap. “We’ve got 200 million SoCs today in autonomous vehicles with long-standing customers,” James Prior, head of marketing at MIPS, told EE Times at CES 2026.
The move to RISC-V
Since its foundational MIPS architecture was introduced in 1985 via the R2000/R3000, MIPS has introduced seven versions of MIPS cores, and since 2022, the eighth generation has been RISC-V. “Our eighth generation of products is our first generation of RISC-V,” Prior said. He referenced the company’s long-standing customer Mobileye, which has already released six generations of its EyeQ product line and recently announced EyeQ7 using the new MIPS RISC-V technology. “EyeQ6 is used in 1,200 different car models across 50 different global OEMs. That’s 75% of ADAS in the actual market.”
Similar to Mobileye, Prior expects the established automotive market to “drain and fill” previous-generation MIPS cores to newer RISC-V cores, especially given the release of its S8200 RISC-V NPUs, which can be uniquely developed using its software-first approach. “We’re seeing the evolution from MIPS the IP provider into MIPS the technology enabler,” he said.
MIPS: a ‘technology enabler’
Prior sees the switch from classic car architectures to zonal and software-defined vehicles as the defining ramp for software RISC-V: “That’s what RISC-V is perfectly suited for—software-defined architectures.” The concept of software architects driving silicon decisions has grown in the embedded world, where customers are increasingly requiring their partners to help solve specific workload problems rather than purchase generic IP. “The model of buying one big chip and having some little chips around it to make a platform is outdated; it doesn’t scale well,” Prior said.
When discussing MIPS moving toward technology enablement, he was largely referencing the company’s Atlas Explorer virtual platform: “Atlas Explorer lets you customize your CPU core, see the performance in real time, much earlier than when you’d have the device in hand.” The platform encourages software-hardware co-design by first modeling the workload, identifying bottlenecks, and fixing them using customer instructions on the software side. Then tune the silicon by customizing the core, adjusting the number of cores and IPs, and adjusting the analog components within the design.
Prior brought out a key differentiator from Arm—the largest IP provider focused on advanced technology nodes in high-volume consumer markets from data centers to smartphones—while MIPS is carving out the physical AI space. “We’re able to support advanced technology nodes, but we’re focusing on them for the autonomous edge, the applications that need on-device deterministic processing and mission-critical functions.”
In fact, he believes that RISC-V will be “over-indexed” in physical AI markets due to this core philosophical difference between the licensed, fixed-core design and a modular, extensible architecture. Workload-specific optimizations can potentially shift from heterogeneous solutions that pair an MCU with a DSP to an approach that keeps everything within the single, unified ISA.
Safety-critical automotive
While this may seem advantageous at first glance, it shouldn’t diminish the importance of reliability and determinism. These requirements are often found in embedded edge applications, especially in automotive, where OEMs aim for proven solutions. However, according to Prior, MIPS has addressed this. He said, “We were the first to have a RISC-V multi-threaded processor core certified for [ISO 26262] ASIL-B.”
Another critical aspect is the switch from simultaneous multi-threading (SMT) to real-time multi-threading (RTMT), uniquely suited to physical AI workloads where determinism and low latency matter more than throughput. In SMT, a single physical core can execute multiple threads at the same time by sharing execution resources, where stalled threads do not dominate the core’s execution units, and another thread can opportunistically use that hardware. The shared execution resources keep the pipeline busy; however, there is overhead involved, e.g., cache core flush, save state, and load new, which will impact determinism.
RTMT instead builds dedicated hardware resources for each thread, so context-switching is instantaneous. “When an event happens, and you have to pause your software and switch contexts, it’s as fast as possible because we’ve got the hardware resources right there.” When, for example, a sensor fires an interrupt, the core will not have to stop, save everything, and load the interrupt handler. Instead, it switches to the thread already configured to handle the event, with dedicated registers already loaded. According to Prior, SMT can switch contexts in microseconds, whereas RTMT can switch contexts on the order of picoseconds, although the company’s website mentions only sub-10-µs control loops with its M8500 general-purpose MCUs.
A GlobalFoundries company
Prior said that MIPS’s GlobalFoundries (GF) acquisition in July last year allowed the company to accelerate development on S8200 NPUs. “We had two problems: building a product portfolio and building a company. We solved problem No. 2 by instantly plugging into GF.”
There is still foundry flexibility under GF, though, where customers such as ForwardEdge ASIC, a subsidiary of Lockheed Martin, selected the Intel 18A process for its MIPS S8200 for use in autonomous platforms. “We wouldn’t be much of an IP business if we didn’t support TSMC,” Prior said.
The company potentially has a unique competitive advantage as an IP provider that has access to a foundry. “There’s not another IP provider, apart from Intel, that has access to a foundry, so we can go and build our IP and make a developer platform way cheaper than anybody else can, way more effective, way more optimized, because we’re the only guys that can go from RISC-V IP core to transistor back to IP core and micro-architecture,” Prior said.
The same can be said for GF, especially with the recent Synopsys ARC acquisition, where the pure-play foundry is now positioning itself as a vertically integrated physical AI platform by essentially offering the full stack in-house from manufacturing to IP. ARC’s billions of annual shipments are concentrated in flash storage controllers—SSDs, USB drives, SD cards—where they dominate the embedded processor market. The portfolio also spans ultra-low-power IoT, embedded vision, neural processing, and the ASIL-D-rated ARC-V.
Granted, the conversation with MIPS occurred before the news of the acquisition was released; however, these portfolios appear mostly complementary, allowing GF to capture more of the value chain, including IP licensing and manufacturing revenue per design win. So instead of competing with TSMC on cutting-edge nodes below 7 nm, their manufacturing business focuses on mature technologies, e.g., 12-nm FinFET, 22-nm FD-SOI, RF SOI, SiPh, GaN, SiGe, etc., in proven platforms through vertical integration—reducing total costs for customers.
https://www.eetimes.com/mips-globalfoundries-bet-on-physical-ai/
